This invention pertains to timing signal generation, particularly suitable for use in a computerized test system such as that used for testing integrated circuits.
Means for testing integrated circuits are well known in the art. Modern systems include the use of a digital computer which is programmed to generate specific timing signals for application to a device under test (DUT), and appropriate supply, ground, and other voltages required to simulate the actual operating environment of the DUT. As integrated circuit devices grow larger, the need for more accurate, high speed, inexpensive, and repeatable testing techniques, including means for generating the appropriate timing signals, are required. However, in order to obtain high speed, accurate, and repeatable timing signals, techniques have been employed which become increasingly expensive. Furthermore, many of these techniques, even though expensive, are not really as accurate or repeatable as desired.
One such prior art technique for generating timing signals is described in U.S. Pat. No. 4,231,104 issued Oct. 28, 1982, St. Clair. St. Clair provides that an oscillator, such as a crystal oscillator, is used to provide a clock signal. This clock signal is applied to a period generator circuit, which allows a period of desired length to be generated from the crystal oscillator. St. Clair utilizes a counter to count an integral number of clocks from the crystal oscillator and a delay line to interpolate between clock cycles in order that the period generated need not have a period equal to an integral number of clock cycles of the crystal oscillator. Furthermore, St. Clair, due to the manner in which he generates his timing signal edges, requires the period generated to provide two output signals: T.sub.syn, which is a delayed version of the crystal oscillator clock signal, and T.sub.out, the actual period signal. St. Clair requires the use of a delay line in order to provide these signals T.sub.syn and T.sub.out so that they are interpolated and thus not necessarily aligned with the crystal oscillator clock edge. Such delay lines typically comprise a rather long trace on a printed circuit board, thus requiring a rather large area on the printed circuit board and thus being expensive. Other types of delay lines which can be used are lumped inductor capacitor ladders or networks, which again are expensive. Furthermore, regardless of the type of delay line used, the delay line circuit must be carefully calibrated, thereby requiring additional calibration circuitry which is expensive and in itself difficult to maintain. Furthermore, even once a delay line circuit is calibrated, it is still subject to errors which are dependent on duty cycle and which cannot be removed by further calibration. The delay line circuit can easily drift out of calibration requiring extensive maintenance of the circuit for recalibration, and errors may be induced due to "jitter" caused by attenuation of the timing signal with an attendant alteration of the rise and fall times, and cross talk between the timing signal passing through the delay line and surrounding signals in the system. Yet another problem with prior art systems is their need to "broadcast" variable length T.sub.syn signal to many locations in a typical, large system, with inherent degradation in timing occurring due to transmission line effects, and variations among the several transmission lines used for "broadcasting" to various locations within the system.
St. Clair also provides a waveform generator which receives as input signals the T.sub.syn and T.sub.out signals from the period generator. The waveform generator of St. Clair FIG. 2 includes two edge generator circuits and a wave formatter (60). Each of St. Clair's edge generators includes memory which defines the placement of the edge within a period based on coincidence with a counter contained within the waveform generator. Furthermore, for each edge generator St. Clair provides an additional delay line in order to place the edge at a point which is interpolated between points provided by the period generator. As previously mentioned, these delay line circuits have severe disadvantages. Furthermore, in St. Clair's structure, the delay lines contained within the waveform generator have the potential of delaying the signal up to two times the period of the crystal oscillator. This introduces additional error.
An additional disadvantage to St. Clair's waveform generator is the fact that each edge generator within the waveform generator can provide only a single edge during a given period.
In addition, by the use of the various delay lines in St. Clair, timing signals within the circuit are not synchronized with the crystal oscillator, thereby making design, calibration, and debugging of such a timing system quite complex and frustrating.